1. Field of the Invention
The present invention relates to a memory controller. More particularly, this invention relates to the calibration of a memory controller which is configured to receive a data strobe signal from a memory.
2. Background
It is known to provide a memory controller which is configured to control memory accesses to a memory device, wherein the memory controller and memory device can exchange a data strobe signal which accompanies a data signal transmitted as part of those memory accesses and indicates the points at which those data signals should be sampled in order to be correctly interpreted. When non active the data strobe signal line (or rather lines since this is typically differential pair of data strobe signals) is/are kept in a high impedance state which allows the data strobe signal line to be driven either by a memory controller or by the memory device as required. During a read memory access, the data strobe signal line is driven by a memory device, preceded by a short preamble before any data is transmitted to allow the opening of a gating signal in the memory controller. This gating signal is generated by the memory controller and the received data strobe signal is only interpreted as valid by the memory controller when the gating signal is asserted. This avoids any stray noise causing the data signal receiver to interpret spurious signals as a valid input.
Accordingly, the timing with which the gating signal is generated with respect to the data strobe signal is vital for the correct reception of data during a memory read access. If the gating signal begins too early then noise on the data strobe signal line could result in incorrect data being interpreted at the receiver. Conversely if the gating signal begins too late then genuine transmitted data will be missed.
As contemporary memory systems progress to higher operating frequencies the inherent system jitter and uncertainties can mean that the setting of the timing of the gating signal is a significant challenge which may require laborious user intervention. For example, in a DDR3 memory system operating at 2133 Mbps, the opening preamble of a data transmission is only 840 ps long, whilst typical DRAM uncertainty is +/−100 ps, with a further removal of 80 ps (in the worst case scenario) leaving only a limited time window in which the opening of the gating signal must be placed.
Accordingly it would be desirable to provide an improved technique for determining the relative timing of the gating signal with respect to the data strobe signal.